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Wafers for Automotive and other Key applications using Memories, embedded in Ulsi Processors

05/2018 – 04/2021
Project Name:
Wafers for Automotive and other Key applications using Memories, embedded in Ulsi Processors
Project No.:

About project

The WaKeMeUP project objective is to set-up a pilot line for advanced microcontrollers with embedded non-volatile memory, design and manufacturing for the prototyping of innovative applications for the smart mobility and smart society domains.

Within the WAKeMeUP project IMA has dealt with new generation of high performance microcontrollers with high level of functional integration. IMA focused on high reliability, safety and responsivity of embedded systems and applications. Single-core and dual-core microcontrollers’ modules and demonstrators were designed and evaluated.

Final technological demonstrator was based on a dual-core microcontroller platform from ST Microelectronics. The STM32H755 dual-core MCU with core frequency up to 480 MHz represents a complex high performance system with high level of functional integration. It consists of a “big” high-speed Cortex M7 core which was used to run a Web server utilizing LwIP with RTOS. The “small” Cortex M4 core is running a non-RTOS program realizing the low-latency real time data acquisition (ADC+GPIO with additional sensors communicating via I2C) and allows a real-time process control capabilities. The combination of non-deterministic Ethernet communication and hard real-time requirements put on a M4 core application is a source of a significant increase of complexity for final system integration. The measured data and process control parameters are shared among individual cores. The web server running on the M7 core is generating a dynamic responsive web page with real-time visualization and the possibility of changing parameters of real-time process control via remote web interface. All of the FW functionality for both MCU cores is stored within the embedded 2MB Flash memory and the runtime is utilizing only the embedded RAM shared among individual cores according to requirements of individual processes.

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